1. Field of the Invention
The present invention relates to a start-up circuit, and more particularly to a start-up circuit generating and outputting an initialization signal which initializes an internal circuit of a semiconductor integrated circuit when a power supply voltage is supplied to the internal circuit.
2. Description of the Related Art
FIG. 5 is a circuit diagram showing a conventional start-up circuit 500. The conventional start-up circuit 500 includes a power supply node T1 to which is a power supply voltage VCC, a ground node T2 to which a ground voltage GND, a node n1, a PMOS transistor 501 located between the power supply node T1 and the node n1, a condenser C51 located between the node n1 and the ground node T2, an inverter INV1 having PMOS and NMOS transistors 503 and 505, an inverter INV2 having PMOS and NMOS transistors 507 and 509, and an output node ST. The inverter INV1 is located between the power supply and ground nodes T1 and T2, and receives a signal from the node n1. The inverter INV2 is located between the power supply and ground nodes T1 and T2, and receives an output signal of the inverter INV1.
Charging of the condenser C51 starts when the power supply voltage VCC is supplied to the power supply node T1. Then, a voltage level of the node n1 rises in response to a time constant on the basis of an ON state resistance of the PMOS transistor 501 and a capacity of the condenser C51. Since a charged voltage level of the condenser C51 is low right after the power supply voltage VCC is supplied to the power supply node T1, the voltage level of the node n1 is initially a low (“L”) level. As a result, since the PMOS transistor 503 assumes an ON state and the NMOS 505 assumes an OFF state, an output signal of the inverter INV1 is a high (“H”) level. Therefore, the PMOS transistor 507 of the inverter INV2 assumes an OFF state and the NMOS transistor 509 assumes an ON state, and then an “L” level signal is outputted from the output node ST. Then, the condenser C51 is further charged. A “H” level signal is eventually outputted from the output node ST after the voltage level of the node n1 becomes higher than a threshold voltage level of the inverter INV1.
Accordingly, after the power supply voltage VCC is supplied to the power supply node T1, the voltage level of the output node ST is maintained at an “L” level for a certain period in response to the time constant, and is then switched to an “H” level after the certain period. An initialization of an internal circuit which is connected to the output node ST is performed during the certain period that the voltage level of the output node ST is at the “L” level.
An electrical charge stored in the condenser C51 discharges to the power supply node T1 through the PMOS transistor 501, when a supply of the power supply voltage VCC to the power supply node T1 is (interrupted) stopped.
However, during a discharge of the condenser C51 of the conventional start-up circuit, since the PMOS transistor 501 switches to an off state when a voltage level of the node n1 falls to a threshold voltage level of the PMOS transistor 501, an electrical charge having the threshold voltage level of the PMOS transistor 501 is still held in the condenser C51. Such an electrical charge discharges during a state in which the power supply voltage VCC is disrupted. However, a discharging time of the electrical charge becomes to longer. Also, since the electrical charge stored in the condenser C51 does not discharge quickly when the power supply voltage VCC is disrupted, an electrical potential is held at the node n1. Then, if a supply of the power supply voltage VCC is resumed, the voltage level of the node n1 exceeds the threshold voltage level of the inverter INV1 before initialization of the internal circuit. As a result, an “H” level signal is outputted from the output node ST before the internal circuit can be initialized properly.